In recent years, there has been proposed a radio communication system for executing balanced transmission by balancing transmission speed for uploading with that for downloading between a base station and a personal station by employing a TDMA (Time Division Multiple Access)/TDD (Time Division Duplex communication) system.
In this radio communication system, in a case where a large quantity of data is transmitted from a transmitting side to a receiving side between a base station and a personal station (the personal station includes a personal station, and so forth), the receiving side transmits data of no use back to the transmitting side during reception of the data.
As described above, there is displacement between a balanced transmission speed allocated to uploading and to downloading respectively and a transmission speed suited to data actually transmitted for uploading or for downloading, so that efficiency of utilization in the identical frequency is reduced.
A similar technology to solve the problem described above is disclosed, for instance, in Japanese Patent Laid-Open Publication No. HEI 1-30527. In this publication is disclosed a radio communication system for switching to imbalanced transmission if there is a request for making a transmission speed for uploading imbalanced with that for downloading between a base station and a personal station during balanced transmission of data.
In a radio communication system based on the conventional technology, complicated configuration for controls is required to improve the efficiency in utilizing an identical frequency, so that configuration of the entire system and a processing sequence for transmission between a base station and a personal station become complicated, which reduces transmission efficiency.
Also, in this type of radio communication system based on the conventional technology, a binary counter has generally been applied to regeneration of a clock in each of the transmission areas in the time domain. In this case, when the number of clock signals become large in one frame due to high speed transmission, a large number of counter stages should be set therein according to the number of clock signals. For this reason, circuit scale becomes larger in some cases, and operating speed will be restricted in association with increase of circuit scale, which causes increase in power consumption.